MPPA^® : Multi-Purpose Processor Array

The MPPA^® “manycore” processor is organized as a matrix of 16-core clusters interconnected by a Network-on-Chip. Within each cluster, processorcores share memory, DMA engines, and control logic.

The MPPA^® family scales from 16 to 64 clusters on a single chip. The 1024-core version delivers more than 2 Tera operations per second.

MPPA^® processors also integrate several standard high speed I/O interfaces for simple board & system integration :

• Two 64-bit DDR3 memory controllers for high bandwidth main memory transfers
• Two 40 Gb/s (or up to eight 10 Gb/s) Ethernet controllers for efficient network processing applications
• Two 8-lane PCI Express Gen 3 interfaces for high speed connection to host or system integration
• General purpose serial and parallel I/O for standard multimedia stream exchange
• Four 4 to 8-lane high speed Interlaken interfaces for multi-MPPA^® chip system integration or connection to external FPGAs.

MPPA^® processor cores implement an optimized VLIW (Very Long Instruction Word) instruction set that leverages decades of research & development on processor architecture for embedded systems and digital signal processing (DSP) applications. The MPPA processor instruction set offers:

• 16-bit packed integer arithmetic
• 32- and 64-bit integer arithmetic
• 32- and 64-bit fractional arithmetic
• 32- and 64-bit floating point arithmetic, in full compliance with the IEEE 754-2008 standard

MPPA^® product roadmap