MPPA® 256

Massive computing power

Massive computing power

  • MPPA® has been designed as a scalable solution both at the architecture & chip level, and at the system & integration level. The MPPA® chip family scales from 256 to 1024 cores with a performance of 500 Giga operations per second to more than 2 Tera operations per second.
  • Multiple MPPA® chips can be interconnected on-board through high speed Interlaken interfaces to provide a virtually unlimited processor array. 




System Level Design

System Level Design

  • The AccessCore programming environment offers much higher levels of abstraction for developing complex applications than classical combinations of FPGAs, DSPs and processors.
  • Using the MPPA® dataflow programming environment, system engineers describe the application parallelism (task and/or data) using a C-based syntax, relying on the AccessCore tools to handle mapping, communication and synchronization. AccessCore can be tuned and constrained to reach the desired result in a fraction of the time it would take using historical programming paradigms.
  • It is estimated that typical system development time is reduced by a factor from 2 to 4 with respect to classical development time for FPGAs and ASICs.
  •  Compilation time for MPPA® is also much shorter (a few seconds to a few minutes) than what is common for FPGA mapping (minutes to hours).

 

Integration with industry standards

Industry standard

MPPA® chips have been designed to integrate as simply as possible within existing and future systems:
  • Standard 40mm x 40mm BGA packaging
  • A large number of integrated I/O devices: Ethernet, PCI Express, Serial & Parallel IOs, etc.
  • Use of the C language and support of the standard GNU GCC tool set
  • Support of LINUX for legacy functions and system supervision

 

 

 

Power consumption and cost

Cost

  • MPPA® is using the most advanced CMOS technology (28nm) to deliver the highest processing power with optimized power consumption.
  • Advanced power management features are proposed to application designers to optimize the application power consumption.
  • Small die area is ensured by 28 nm technology.




High performance / mm² of silicon
High performance / Watt
Fast programming solution
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